Yield and performance issues in fault-tolerant WSI array architectures

Yung Yuan Chen*, Sau-Gee Chen, Jiann Cherng Lee

*Corresponding author for this work

研究成果: Conference article

3 引文 斯高帕斯(Scopus)

摘要

In this paper, a simple but efficient reconfiguration algorithm and placement algorithm are proposed to enhance the manufacturing yield of WSI array processors at low performance degradation. The low performance degradation is significant for high-performance WSI arrays. The objective of our reconfiguration strategy is to achieve better utilization of good spares, while also ensuring that the restructured inter-PE communication links do not become so long as to significantly degrade the performance. Monte Carlo simulation is performed to estimate the array yield and to obtain the performance degradation probability distribution for fault patterns with both PE and switch faults. The simulations conducted indicate that the computational time of the algorithms is quite low, therefore the proposed scheme may also be very suitable for certain run-time fault tolerance.

原文English
頁(從 - 到)318-328
頁數11
期刊Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
DOIs
出版狀態Published - 1 一月 1995
事件Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
持續時間: 18 一月 199520 一月 1995

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