Wafer-level bonding/stacking technology for 3D integration

Cheng Ta Ko, Kuan-Neng Chen*

*Corresponding author for this work

研究成果: Article同行評審

136 引文 斯高帕斯(Scopus)

摘要

Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed.

原文English
頁(從 - 到)481-488
頁數8
期刊Microelectronics Reliability
50
發行號4
DOIs
出版狀態Published - 1 四月 2010

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