VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network

Kuo Wei Chang*, Tian-Sheuan Chang

*Corresponding author for this work

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Hardware accelerators for convolution neural networks (CNNs) enable real-time applications of artificial intelligence technology. However, most of the existing designs suffer from low hardware utilization or high area cost due to complex data flow. This paper proposes a hardware efficient vectorwise CNN accelerator that adopts a 3 × 3 filter optimized systolic array using 1-D broadcast data flow to generate partial sum. This enables easy reconfiguration for different kinds of kernels with interleaved input or elementwise input data flow. This simple and regular data flow results in low area cost while attains high hardware utilization. The presented design achieves 99%, 97%, 93.7%, and 94% hardware utilization for VGG-16, ResNet-34, GoogLeNet, and Mobilenet, respectively. Hardware implementation with TSMC 40nm technology takes 266.9K NAND gate count and 191KB SRAM to support 168GOPS throughput while consumes only 154.98mW when running at 500MHz operating frequency, which has superior area and power efficiency than other designs.

原文English
文章編號8854849
頁(從 - 到)145-154
頁數10
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
67
發行號1
DOIs
出版狀態Published - 一月 2020

指紋 深入研究「VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network」主題。共同形成了獨特的指紋。

引用此