Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister, Albert Chin

研究成果: Conference article同行評審

30 引文 斯高帕斯(Scopus)

摘要

We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

原文English
文章編號4418939
頁(從 - 到)333-336
頁數4
期刊Technical Digest - International Electron Devices Meeting, IEDM
DOIs
出版狀態Published - 1 十二月 2007
事件2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
持續時間: 10 十二月 200712 十二月 2007

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