We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
|頁（從 - 到）||333-336|
|期刊||Technical Digest - International Electron Devices Meeting, IEDM|
|出版狀態||Published - 1 十二月 2007|
|事件||2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States|
持續時間: 10 十二月 2007 → 12 十二月 2007