Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming-Dou Ker, Wen Tai Wang

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

原文English
主出版物標題Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面255-258
頁數4
ISBN(電子)9781479999286, 9781479999286
DOIs
出版狀態Published - 25 八月 2015
事件22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan
持續時間: 29 六月 20152 七月 2015

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
2015-August

Conference

Conference22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
國家Taiwan
城市Hsinchu
期間29/06/152/07/15

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