Verification on port connections

Geeng Wei Lee*, Chun Yao Wang, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

研究成果: Conference article

摘要

In a system-on-a-chip (SOC) design, several to hundreds of design blocks or intellectual properties (IPs) are integrated to form a complex function. Prior to verify the functionality of the integrated IPs, it is very important to ensure the correctness of the port connections among these IPs. This paper addresses the problem of verification on port connections while IPs are integrated into a larger block or a system, and presents a new connection model and the corresponding error model for port connections. An algorithm providing the minimum pattern set and a general verification flow used to verify port connections are also proposed.

原文English
頁(從 - 到)830-836
頁數7
期刊Proceedings - International Test Conference
DOIs
出版狀態Published - 1 十二月 2004
事件Proceedings - International Test Conference 2004 - Charlotte, NC, United States
持續時間: 26 十月 200428 十月 2004

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