Unleashing parallelism with minimal test inflation in multi-Threaded test pattern generation

Louis Y.Z. Lin*, Charles H.P. Wen

*Corresponding author for this work

研究成果: Article

1 引文 斯高帕斯(Scopus)

摘要

Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-Threaded test pattern generation called MT-TPG that can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation, hard-fault shuffling (HFS) and concurrent-fault interruption (CFI) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, the potentially-droppable-fault removal (PDFR) and single-pattern parallel-fault simulation (SPPFSim) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, the HFS and CFI can successfully suppress test inflation to < 4% on 17 benchmark circuits; PDFR and SPPFSim can achieve 13.7X speedup using 16 threads on average. As a result, MT-TPG is proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.

原文English
文章編號8456510
頁(從 - 到)49269-49281
頁數13
期刊IEEE Access
6
DOIs
出版狀態Published - 5 九月 2018

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