Unified bit-parallel arithmetic processor using redundant binary representation

Sau-Gee Chen*

*Corresponding author for this work

研究成果: Paper

摘要

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combing the all MSD-first arithmetic operations, a unified arithmetic processor is obtained which can perform division, multiplication, and square-root operations. This unified processor is similar in structure to an array multiplier. It provides three advantages over the conventional arithmetic unit: (1) higher speed, (2) more functional capability, and (3) better area utilization. It is also suitable for VLSI implementation.

原文English
頁面91-96
頁數6
出版狀態Published - 1 十二月 1989
事件Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings - Scottsdale, AZ, USA
持續時間: 22 三月 198924 三月 1989

Conference

ConferenceEighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings
城市Scottsdale, AZ, USA
期間22/03/8924/03/89

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  • 引用此

    Chen, S-G. (1989). Unified bit-parallel arithmetic processor using redundant binary representation. 91-96. 論文發表於 Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings, Scottsdale, AZ, USA, .