Ultra-low power green electronic devices

S. H. Yi, Albert Chin

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Power consumption is the crucial challenge for electronics. To lower the DC leakage power (PDC), we applied the high-κ gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower PDC is obtained at small 0.5-0.9 nm equivalent-oxide-thickness (EOT). The high-κ dielectric also increases the charge controllability of flash memory and decrease the VT disturbance by nearly cells, which improves cell density and cost. The AC power (PAC) can be lowered by using high-mobility Ge CMOS at a lower VD and 3D IC with a small capacitance, from basic physics of PAC equivalent to CVD2f/2.

原文English
主出版物標題Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面285-288
頁數4
ISBN(電子)9781479983636
DOIs
出版狀態Published - 30 九月 2015
事件11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
持續時間: 1 六月 20154 六月 2015

出版系列

名字Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Conference

Conference11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
國家Singapore
城市Singapore
期間1/06/154/06/15

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