Two-step incremental analogue-to-digital converter

Chia-Hung Chen, Y. Zhang, Y. Jung, T. He, J. L. Ceballos, G. C. Temes

研究成果: Article

14 引文 斯高帕斯(Scopus)

摘要

A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.

原文English
頁(從 - 到)307-308
頁數2
期刊Electronics Letters
49
發行號4
DOIs
出版狀態Published - 14 二月 2013

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    Chen, C-H., Zhang, Y., Jung, Y., He, T., Ceballos, J. L., & Temes, G. C. (2013). Two-step incremental analogue-to-digital converter. Electronics Letters, 49(4), 307-308. https://doi.org/10.1049/el.2013.0104