Trapping properties of very thin nitride/oxide gate insulators

J. Y.C. Sun*, M. Arienzo, L. Dori, K. Stein

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The trapping properties of very thin nitride/oxide (10-14nm equivalent SiO2) composite gate insulators and their dependences on gate materials and process conditions are reported. Electron trapping and flatband voltage turn-around effects are more pronounced in these films than in thermal SiO2. They both appear to be dominated by water-related species in the bottom oxide layer when the top nitride layer is thin, similar to the case of thermal SiO2only. For VLSI CMOS applications, trapping and instabilities in the nitride/oxide gate insulator can be minimized by (i) reducing the thickness of the top nitride layer, (ii) using polysilicon gates with proper work functions, and (iii) using appropriate high-temperature dehydration steps after polysilicon gate deposition.

原文English
主出版物標題ESSDERC 1987 - 17th European Solid State Device Research Conference
發行者IEEE Computer Society
頁面841-844
頁數4
ISBN(電子)0444704779
ISBN(列印)9780444704771
出版狀態Published - 1987
事件17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
持續時間: 14 九月 198717 九月 1987

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
國家Italy
城市Bologna
期間14/09/8717/09/87

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