Transient device simulation of trap-assisted leakage in non-volatile memory cell

Hiroshi Watanabe*

*Corresponding author for this work

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

In order to study how a local trap degrades data retention characteristics of floating gate nonvolatile memory cell, a general-purpose Single-Electron Device Simulator (SEDS) developed for Si-dot is improved to carry out a very wide range transient analysis from 0.1 pico-seconds to 10 years. As a result, it is found that the data retention is degraded by the direct tunneling enhanced due to positive charge stored at the trap inside the inter-poly dielectric but not by trap-assisted tunneling.

原文English
頁面45-48
頁數4
DOIs
出版狀態Published - 1 十二月 2008
事件2008 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2008 - Hakone, Japan
持續時間: 9 九月 200811 九月 2008

Conference

Conference2008 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2008
國家Japan
城市Hakone
期間9/09/0811/09/08

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