Threshold voltage design and performance assessment of hetero-channel SRAM cells

Vita Pi Ho Hu*, Ming Long Fan, Pin Su, Ching Te Chuang

*Corresponding author for this work

研究成果: Article

7 引文 斯高帕斯(Scopus)

摘要

Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications.

原文English
文章編號6376153
頁(從 - 到)147-152
頁數6
期刊IEEE Transactions on Electron Devices
60
發行號1
DOIs
出版狀態Published - 1 一月 2013

指紋 深入研究「Threshold voltage design and performance assessment of hetero-channel SRAM cells」主題。共同形成了獨特的指紋。

  • 引用此