The Serial Commutator FFT

Mario Garrido, Shen Jui Huang, Sau-Gee Chen, Oscar Gustafsson

研究成果: Article

17 引文 斯高帕斯(Scopus)

摘要

This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.

原文English
文章編號7425187
頁(從 - 到)974-978
頁數5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
63
發行號10
DOIs
出版狀態Published - 1 十月 2016

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