The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications

Wei Chen Chen*, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

研究成果: Conference contribution

摘要

A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (lDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.

原文English
主出版物標題2010 Silicon Nanoelectronics Workshop, SNW 2010
DOIs
出版狀態Published - 22 十月 2010
事件2010 15th Silicon Nanoelectronics Workshop, SNW 2010 - Honolulu, HI, United States
持續時間: 13 六月 201014 六月 2010

出版系列

名字2010 Silicon Nanoelectronics Workshop, SNW 2010

Conference

Conference2010 15th Silicon Nanoelectronics Workshop, SNW 2010
國家United States
城市Honolulu, HI
期間13/06/1014/06/10

指紋 深入研究「The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications」主題。共同形成了獨特的指紋。

引用此