The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices

Wen Tsung Huang, Yiming Li*

*Corresponding author for this work

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.

原文English
主出版物標題International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
發行者Institute of Electrical and Electronics Engineers Inc.
頁面281-284
頁數4
ISBN(電子)9781479952885
DOIs
出版狀態Published - 20 十月 2014
事件2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, Japan
持續時間: 9 九月 201411 九月 2014

出版系列

名字International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
國家Japan
城市Yokohama
期間9/09/1411/09/14

指紋 深入研究「The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices」主題。共同形成了獨特的指紋。

引用此