The impact of device scaling and power supply change on CMOS gate performance

Kai Chen*, H. Clement Wann, Ping K. Ko, Chen-Ming Hu

*Corresponding author for this work

研究成果: Article同行評審

45 引文 斯高帕斯(Scopus)

摘要

Based a new empirical mobility model that's solely dependent on V gs , V t , and T or and a corresponding saturation drain current (I dsat ) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V dd (for low power applications) if V t can be lowered.

原文English
頁(從 - 到)202-204
頁數3
期刊IEEE Electron Device Letters
17
發行號5
DOIs
出版狀態Published - 1 五月 1996

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