In this paper, a new structure of 8-bit CMOS pipelined analog-to-digital converter (ADC) is proposed and analyzed. In order to achieve a high conversion rate, the proposed new structure adopts voltage-mode open-loop sampling circuit and current-mode circuits to perform subtraction, sub-DAC operation, and comparison. Due to current-mode subtraction operation, the close-loop circuit can be avoided to improve the speed performance. Moreover, current steering sub-DAC is used to enhance the sub-DAC speed. From the simulation results on the demonstrative example, the proposed pipelined ADC architecture can achieve 8-bit accuracy with a sampling rate up to 71.4MS/s when the input signal frequency is 10M Hz. The power dissipation of the pipelined ADC is 205mW at the conversion rate of 71.4 MS/s with a single 3.3V power supply and 1P5M 0.25μm CMOS process. The proposed structure can reach a higher speed if the voltage-sampling delay is reduced.
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 一月 2002|
|事件||2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States|
持續時間: 26 五月 2002 → 29 五月 2002