The design of 8-channel CMOS area-efficient low-power current-mode analog front-end amplifier for EEG signal recording

Ya Syuan Sung, Wei Ming Chen, Chung-Yu Wu

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop (OCCL). The AFEA employs CCGM with only 2pF input capacitance to eliminate the electrode dc offset (EDO). The current-mode topology is adopted in the design of CCGMs, CMBPF s, and PCGAs to reduce the power consumption. The shared OCCL is designed to eliminate the output offset of CCGM, CMBPF and PCGA. The AFEA is designed and fabricated in 180-nm CMOS technology and the core area occupies only 1mm2. The measured maximum gain is 82 dB. The measured input-referred noise is 3.34μVrms within the bandwidth of 0.5-100 Hz. The measured maximum power consumption is 7.85 μW per channel under power supply of 1.2 V. The fabricated AFEA is applied to record the human EEG signal successfully.

原文English
主出版物標題ISCAS 2016 - IEEE International Symposium on Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
頁面530-533
頁數4
ISBN(電子)9781479953400
DOIs
出版狀態Published - 29 七月 2016
事件2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
持續時間: 22 五月 201625 五月 2016

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2016-July
ISSN(列印)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
國家Canada
城市Montreal
期間22/05/1625/05/16

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