Testing retention flip-flops in power-gated designs

Hao Wen Hsu, Shih Hua Kuo, Wen Hsiang Chang, Shi Hao Chen, Ming Tung Chang, Chia-Tso Chao

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

原文English
主出版物標題Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs
出版狀態Published - 14 八月 2013
事件2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
持續時間: 29 四月 20131 五月 2013

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
國家United States
城市Berkeley, CA
期間29/04/131/05/13

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