Test structure on SCR device in waffle layout for RF ESD protection

Ming-Dou Ker*, Chun Yu Lin

*Corresponding author for this work

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.

原文English
主出版物標題2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
頁面196-199
頁數4
DOIs
出版狀態Published - 27 九月 2007
事件2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, Japan
持續時間: 19 三月 200722 三月 2007

出版系列

名字IEEE International Conference on Microelectronic Test Structures

Conference

Conference2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
國家Japan
城市Bunkyo-ku
期間19/03/0722/03/07

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