For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.
|出版狀態||Published - 21 七月 2003|
|事件||IEEE International Conference on Microelectronic Test Structures - Monterey, CA, United States|
持續時間: 17 三月 2003 → 20 三月 2003
|Conference||IEEE International Conference on Microelectronic Test Structures|
|期間||17/03/03 → 20/03/03|