Test generation and site of fault for combinational circuits using logic Petri Nets

Jui I. Tsai*, Ching Cheng Teng, Ching Hung Lee

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

In this paper, we propose a novel Petri Net model for solving test generation and site of fault and fired logical value for combinational circuits. In order to improve the logic fault efficiency, the transitions of general Petri Nets (PNs) are modified according to the critical of truth table, called Logic Petri Net LPN. The LPN model can transfer complexity circuit problem to a local adjacent place and transition relational problem. Therefore, the site of fault and fired logical value problem is simplified and clearly. The LPN model has the properties of Boolean algorithm, collapsing fault with clear physical concepts, fast calculation speed, and high veracity. The approach contains site of a fault and fired logical value reasoning algorithm and test vector generation reasoning algorithm. Two examples are shown to demonstrate the effectiveness of our approach.

原文English
主出版物標題2006 IEEE International Conference on Systems, Man and Cybernetics
發行者Institute of Electrical and Electronics Engineers Inc.
頁面91-96
頁數6
ISBN(列印)1424401003, 9781424401000
DOIs
出版狀態Published - 2006
事件2006 IEEE International Conference on Systems, Man and Cybernetics - Taipei, Taiwan
持續時間: 8 十月 200611 十月 2006

出版系列

名字Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
1
ISSN(列印)1062-922X

Conference

Conference2006 IEEE International Conference on Systems, Man and Cybernetics
國家Taiwan
城市Taipei
期間8/10/0611/10/06

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