This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8- μ bipolar process for TVS chips. The I - V curves of the TVS and CAN transceiver chip are evaluated by the transmission line pulsing system with the pulse width of 100 ns. The breakdown voltage of the bi-directional TVS chips and CAN transceiver chip are higher than ±80 V compared with the ±70 V fault voltage tolerance requirement. The clamping voltage of the TVS device is lower than ±130 V to discharge ESD current before the CAN transceiver chip breakdown for effective ESD protection. The design target of parasitic inductance by bonding wires is calculated to meet the clamping voltage requirement. The CAN bus transceiver IC with TVS chips co-packaged has been evaluated to pass the IEC61000-4-2 contact ±15-kV stress without any hardware damages and latch-up issues.
|頁（從 - 到）||570-576|
|期刊||IEEE Transactions on Device and Materials Reliability|
|出版狀態||Published - 1 九月 2017|