Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*Corresponding author for this work

研究成果: Article

13 引文 斯高帕斯(Scopus)

摘要

New electrostatic discharge (ESD) clamp devices for using in power-rail ESD clamp circuits with the substrate-triggered technique are proposed to improve ESD level in a limited silicon area. The parasitic n-p-n and p-n-p bipolar junction transistors (BJTs) in the CMOS devices are used to form the substrate-triggered devices for ESD protection. Four substrate-triggered devices are proposed and investigated in this work, which are named as the substrate-triggered lateral BJT, the substrate-triggered vertical BJT, the substrate-triggered double BJT, and the double-triggered double BJT. An RC-based ESD-detection circuit is used to generate the triggering current to turn on the proposed substrate-triggered devices. In order to trigger on the parasitic bipolar transistors more effectively, the symmetric multiple-cell square-type layout method is used to realize these substrate-triggered devices. The power-rail ESD clamp circuits with such substrate-triggered devices have been fabricated in a 0.6-μm CMOS process. Experimental results have shown that the substrate-triggered device with double-BJT structure can provide 200% higher ESD robustness in per silicon area, as compared to the NMOS with the traditional gate-driven design.

原文English
頁(從 - 到)721-734
頁數14
期刊Solid-State Electronics
46
發行號5
DOIs
出版狀態Published - 1 五月 2002

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