Structural approach for performance driven ECC circuit synthesis

Chau-Chin Su*, Kathy Y. Chen, Shyh-Jye Jou

*Corresponding author for this work

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.

原文English
頁面89-94
頁數6
DOIs
出版狀態Published - 1 一月 1997
事件Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
持續時間: 28 一月 199731 一月 1997

Conference

ConferenceProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
城市Chiba, Jpn
期間28/01/9731/01/97

指紋 深入研究「Structural approach for performance driven ECC circuit synthesis」主題。共同形成了獨特的指紋。

引用此