Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm tigh-performance strained-Si device application

Chien-Hao Chen*, TL Lee, Tuo-Hung Hou, C.L. Chen, CC Chen, J. W. Hsu, KL Cheng, YH Chiu, H. J. Tao, Y. Jin, C. H. Diaz, SC Chen, MS Liang

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional similar to10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

原文English
主出版物標題2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
發行者IEEE
頁面56-57
頁數2
ISBN(列印)0-7803-8289-7
出版狀態Published - 六月 2004
事件Symposium on VLSI Technology - Honolulu
持續時間: 15 六月 200417 六月 2004

Conference

ConferenceSymposium on VLSI Technology
城市Honolulu
期間15/06/0417/06/04

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