Statistical circuit characterization for deep-submicron CMOS designs

James Chen*, Michael Orshansky, Chen-Ming Hu, C. P. Wan

*Corresponding author for this work

研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)


Aggressive scaling of CMOS MOSFET gate lengths is halving minimum device channel lengths every 4 to 6 years. This brings an increase in deep submicron device performance sensitivity to manufacturing variations. Its impact on highly-integrated, system-on-a-chip designs needs assessment to ensure first-pass silicon and adequate yield. Standard simulations to assess these impacts are performed at SPICE simulation level and rely upon a multivariate statistical technique called principal component analysis. This method is popular because it reduces the large number of correlated SPICE model parameters characteristic of current deep-submicron models into few statistically independent factors which can then be generated by Monte Carlo simulation.

頁(從 - 到)90-91
期刊Digest of Technical Papers - IEEE International Solid-State Circuits Conference
出版狀態Published - 1 一月 1998
事件Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA
持續時間: 5 二月 19987 二月 1998

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