Static power analysis for power-driven synthesis

S. Y. Yuan*, Ke-Horng Chen, J. Y. Jou, S. Y. Kuo

*Corresponding author for this work

研究成果: Article

摘要

A new static power analysis method for CMOS combinational circuits is presented. This approach integrates the simulation-based method and the probabilistic method, and can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus suitable for performing power estimation in the synthesis environment for power optimisation. To the best of our knowledge, this is the first attempt to develop a systematic way to symbolically represent the relationships between the primary inputs and the power consumption at every internal node of a circuit. Furthermore, by using the existing piecewise linear delay model, as well as the proposed algorithm, this novel method is also very accurate and efficient. For a set of benchmark circuits, the experimental results show that the power estimated by our technique is within 5% error as compared with that by the exact SPICE simulation, while the execution speed is more than four orders of magnitude faster.

原文English
頁(從 - 到)89-95
頁數7
期刊IEE Proceedings: Computers and Digital Techniques
145
發行號2
DOIs
出版狀態Published - 1 一月 1998

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