Spur-reduction frequency synthesizer exploiting randomly selected PFD

Te Wen Liao*, Jun Ren Su, Chung-Chih Hung

*Corresponding author for this work

研究成果: Article同行評審

12 引文 斯高帕斯(Scopus)

摘要

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of-93 dBc Hz with a 600-kHz offset frequency and reference spurs below-72 dBc.

原文English
文章編號6176004
頁(從 - 到)589-592
頁數4
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
21
發行號3
DOIs
出版狀態Published - 1 一月 2013

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