Spatial and energetic distribution of border traps in the dual-layer HfO2/Si O2 high- k gate stack by low-frequency capacitance-voltage measurement

Wei Hao Wu*, Bing-Yue Tsui, Mao Chieh Chen, Yong Tian Hou, Yin Jin, Hun Jan Tao, Shih Chang Chen, Mong Song Liang

*Corresponding author for this work

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)

摘要

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high- k gate dielectrics, and these high- k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the Hf O2 Si O2 high- k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high- k metal-oxide-semiconductor capacitors with n -type Si substrate.

原文English
文章編號162911
期刊Applied Physics Letters
89
發行號16
DOIs
出版狀態Published - 25 十月 2006

指紋 深入研究「Spatial and energetic distribution of border traps in the dual-layer HfO<sub>2</sub>/Si O<sub>2</sub> high- k gate stack by low-frequency capacitance-voltage measurement」主題。共同形成了獨特的指紋。

引用此