Soft error rate reduction using redundancy addition and removal

Kai-Chiang Wu*, Diana Marculescu

*Corresponding author for this work

研究成果: Conference contribution

22 引文 斯高帕斯(Scopus)

摘要

Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, circuit reliability has become more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. In this paper, we propose a novel framework based on redundancy addition and removal (RAR) for soft error rate (SER) reduction. Several metrics and constraints are introduced to guide our proposed framework towards SER reduction in an efficient manner. Experimental results show that up to 70% reduction in output failure probability can be achieved with relatively low area overhead.

原文English
主出版物標題2008 Asia and South Pacific Design Automation Conference, ASP-DAC
頁面559-564
頁數6
DOIs
出版狀態Published - 21 八月 2008
事件2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
持續時間: 21 三月 200824 三月 2008

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
國家Korea, Republic of
城市Seoul
期間21/03/0824/03/08

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  • 引用此

    Wu, K-C., & Marculescu, D. (2008). Soft error rate reduction using redundancy addition and removal. 於 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (頁 559-564). [4484014] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4484014