Single-ended frequency divider with moduli of 256-271

Sheng Che Tseng*, Chin-Chun Meng, Shao Yu Li, Jen Yi Su, Guo Wei Huang

*Corresponding author for this work

研究成果: Article同行評審

摘要

This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 27] in the standard 0.35-μm 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about - 10 dBm and the lowest level is - 25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 × 0.7 mm2.

原文English
頁(從 - 到)2096-2100
頁數5
期刊Microwave and Optical Technology Letters
48
發行號10
DOIs
出版狀態Published - 1 十月 2006

指紋 深入研究「Single-ended frequency divider with moduli of 256-271」主題。共同形成了獨特的指紋。

引用此