Simultaneous buffer-sizing and wire-sizing for clock trees based on lagrangian relaxation

Yu-Min Lee, Charlie Chung Ping Chen*, Yao Wen Chang, D. F. Wong

*Corresponding author for this work

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

原文English
頁(從 - 到)587-594
頁數8
期刊VLSI Design
15
發行號3
DOIs
出版狀態Published - 1 一月 2002

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