Simulation of grain-boundary induced Vth variability in stackable NAND flash using a Voronoi approach

Ching Wei Yang, Shao Heng Chao, Pin Su

研究成果: Conference contribution同行評審

摘要

In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.

原文English
主出版物標題2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012
頁面12-15
頁數4
DOIs
出版狀態Published - 1 十二月 2012
事件2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012 - Singapore, Singapore
持續時間: 31 十月 20122 十一月 2012

出版系列

名字2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012

Conference

Conference2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012
國家Singapore
城市Singapore
期間31/10/122/11/12

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