Simulation and investigation of random grain-boundary-induced variabilities for stackable NAND flash using 3-D voronoi grain patterns

Ching Wei Yang, Pin Su

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (H ch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation.

原文English
文章編號6766781
頁(從 - 到)1211-1214
頁數4
期刊IEEE Transactions on Electron Devices
61
發行號4
DOIs
出版狀態Published - 1 一月 2014

指紋 深入研究「Simulation and investigation of random grain-boundary-induced variabilities for stackable NAND flash using 3-D voronoi grain patterns」主題。共同形成了獨特的指紋。

引用此