Simulating hot-carrier effects on circuit performance

Chen-Ming Hu*

*Corresponding author for this work

研究成果: Article

15 引文 斯高帕斯(Scopus)

摘要

Hot carriers cause charge trapping in the gate oxide of MOSFETs and generate interface traps at Si/SiO2 interfaces of MOSFETs and bipolar transistors. Models for N-channel and P-channel MOSFETs and for bipolar transistor degradations have been developed and implemented in an IC reliability simulator BERT. Several comparisons between simulation results and measurements are shown. There remain to be answered questions concerning the presence of excess degradation when the stressing signal frequency is high.

原文English
文章編號146
期刊Semiconductor Science and Technology
7
發行號3 B
DOIs
出版狀態Published - 1 十二月 1992

指紋 深入研究「Simulating hot-carrier effects on circuit performance」主題。共同形成了獨特的指紋。

  • 引用此