Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design

Jam Wem Lee*, Yi-Ming Li, Howard Tang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.

原文English
主出版物標題Proceedings of the International Conference on VLSI, VLSI 03
編輯H.R. Arbania, L.T. Yang
頁面251-257
頁數7
出版狀態Published - 一月 2003
事件Proceedings of the International Conference on VLSI, VLSI'03 - Las Vegas, NV, United States
持續時間: 23 六月 200326 六月 2003

出版系列

名字Proceedings of the International Conference on VLSI

Conference

ConferenceProceedings of the International Conference on VLSI, VLSI'03
國家United States
城市Las Vegas, NV
期間23/06/0326/06/03

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