In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.