Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device with 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery

Korok Chatterjee*, Sangwan Kim, Golnaz Karbasian, Ava J. Tan, Ajay K. Yadav, Asif I. Khan, Chen-Ming Hu, Sayeef Salahuddin

*Corresponding author for this work

研究成果: Article同行評審

46 引文 斯高帕斯(Scopus)

摘要

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of >10^{10} read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

原文English
文章編號8025570
頁(從 - 到)1379-1382
頁數4
期刊IEEE Electron Device Letters
38
發行號10
DOIs
出版狀態Published - 1 十月 2017

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