SBD layout optimization with effect of N-well to p-substrate pn junctions in 0.18 μm CMOS process

Wei Ling Chang, Chinchun Meng, Guo Wei Huang

研究成果: Conference contribution同行評審

摘要

The effect of layout on silicon SBD in CMOS process is studied in this paper. The size of anode area not only affects the series resistance and SBD junction capacitance but also causes serious parasitic effect from cathode to the p-substrate. Typically, an SBD of a small unit anode has a better cut-off frequency than that of a large unit anode. The cutoff frequency of a small anode Schottky diode is about 700 GHz in a standard 0.18 μm CMOS process. However, a SBD with a small unit anode is prone to the effect of p-substrate to N-well pn junction capacitor. This paper has characterized SBDs of different anode sizes with bottom and side-wall effect of p-substrate to N-well to select an optimal unit-anode area by reducing the substrate effect and providing sufficient fT for high frequency applications.

原文English
主出版物標題2016 Asia-Pacific Microwave Conference, APMC 2016 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509015924
DOIs
出版狀態Published - 17 五月 2017
事件2016 Asia-Pacific Microwave Conference, APMC 2016 - Aerocity, New Delhi, India
持續時間: 5 十二月 20169 十二月 2016

出版系列

名字Asia-Pacific Microwave Conference Proceedings, APMC
0

Conference

Conference2016 Asia-Pacific Microwave Conference, APMC 2016
國家India
城市Aerocity, New Delhi
期間5/12/169/12/16

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