RF-interconnect for future network-on-chip

Sai Wang Tam*, Eran Socher, Mau-Chung Chang, Jason Cong, Glenn D. Reinman

*Corresponding author for this work

研究成果: Chapter同行評審

13 引文 斯高帕斯(Scopus)

摘要

In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). It is projected that communication via NoC is one of the primary limiters to both performance and power consumption. To mitigate such problems, we explore the use of multiband RF-interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission and reconfigurable bandwidth. At the same time, we investigate the CMOS mixed-signal circuit implementation challenges for improving the RF-I signaling integrity and efficiency. Furthermore, we propose a micro-architectural framework that can be used to facilitate the exploration of scalable low power NoC architectures based on physical planning and prototyping.

原文English
主出版物標題Low Power Networks-On-Chip
發行者Springer
頁面255-280
頁數26
ISBN(列印)9781441969101
DOIs
出版狀態Published - 1 十二月 2011

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