Resistive Approach for Extraction of Bias-Dependent Parasitic Resistance, Mobility and Virtual Gate Length in GaN HEMT

Pragyey Kumar Kaushik*, Sankalp Kumar Singh, Ankur Gupta, Ananjan Basu, Edward Yi Chang

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

In this work, we introduce a resistive approach to extract various device performance parameters such as contact resistance, mobility and effective gate length. Without passivation of the un-gated region, HEMT device leads to forming of an extra gate length either side of gate called virtual gate length (dLG). Carrier mobility (µC) of 2DEG and dLG also depends upon VGS (gate bias). The depleted channel also reduces the device current causing a significant increase in source/drain resistance (RS/RD).

原文English
主出版物標題2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面117-118
頁數2
ISBN(電子)9781728197357
DOIs
出版狀態Published - 六月 2020
事件2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
持續時間: 13 六月 202014 六月 2020

出版系列

名字2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
國家United States
城市Honolulu
期間13/06/2014/06/20

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