Reliability study of MANOS with and without a SiO2 buffer layer and BE-MANOS charge-trapping NAND flash devices

Chien Wei Liao*, Sheng Chih Lai, Hang Ting Lue, Ming Jui Yang, Chin Yen Shen, Yi Hsien Lue, Yu Fong Huang, Jung Yu Hsieh, Szu Yu Wang, Guang Li Luo, Chao-Hsin Chien, Kuang Yeu Hsieh, Rich Liu, Chih Yuan Lu

*Corresponding author for this work

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al 2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.

原文English
主出版物標題2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
頁面150-151
頁數2
DOIs
出版狀態Published - 1 十二月 2009
事件2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 - Hsinchu, Taiwan
持續時間: 27 四月 200929 四月 2009

出版系列

名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
國家Taiwan
城市Hsinchu
期間27/04/0929/04/09

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