Recent research in clock power saving with multi-bit flip-flops

Po-Hung Lin*, Chih Cheng Hsu, Yao Tsung Chang

*Corresponding author for this work

研究成果: Conference contribution同行評審

8 引文 斯高帕斯(Scopus)

摘要

In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption of the clock network usually dominates the dynamic power of the chip due to its highest switching rate. To effectively minimize the power consumption of the clock network, recent studies have been investigating the usage of multi-bit flip-flops (MBFFs). This paper presents the advantages of applying MBFFs, introduces various MBFF design flows, surveys key techniques for design optimization with MBFFs, and provides some future research directions in clock power saving with MBFFs.

原文English
主出版物標題54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
出版狀態Published - 13 十月 2011
事件54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
持續時間: 7 八月 201110 八月 2011

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Conference

Conference54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
國家Korea, Republic of
城市Seoul
期間7/08/1110/08/11

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