The medium-level part of a real-time robot vision system involves many subsystems which combine both intensive arithmetic computations and complex decision-making. Moreover, recursive loops typically limit the throughput. Therefore, it is believed that these subsystems can only be efficiently realized within the required throughput specs by developing a VLSI ASIC. This applies also for the regularity detection unit which is the main topic discussed. During the architecture design, several tasks have to be addressed. Starting from the original signal flow graph, the dedicated I/O blocks and the customized, distributed off- and on-chip storage units have been derived. A number of time-multiplexed application-specific data-paths have been defined, optimized towards communication with the memories and towards maximal hardware-sharing within the throughput spec. They exploit the concurrency inherent in the algorithm and are balanced in terms of pipeline sections to increase the clock period achievable. In order to solve the timing bottle-neck in the steering of this complex (partly programmable) data-path organization, a hierarchically partitioned controller is constructed.
|頁（從 - 到）||1493-1496|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 十二月 1990|
|事件||1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA|
持續時間: 1 五月 1990 → 3 五月 1990