Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

Her-Ming Chiueh, Chia Hsiang Yang, Charles H.P. Wen, Chao Guang Yang, Po Hao Chien, Ching Yang Hung, Yu Jui Chen, Yao Pin Wang, Chin Fong Chiu, Jer Lin

研究成果: Conference contribution同行評審

摘要

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET \lt 101.5 MeV-cm {2} / mg), validating the effectiveness of the methodology.

原文English
主出版物標題2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728160832
DOIs
出版狀態Published - 八月 2020
事件2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan
持續時間: 10 八月 202013 八月 2020

出版系列

名字2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
國家Taiwan
城市Hsinchu
期間10/08/2013/08/20

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