Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

Her-Ming Chiueh; Chia Hsiang Yang; Charles H.P. Wen; Chao Guang Yang; Po Hao Chien; Ching Yang Hung; Yu Jui Chen; Yao Pin Wang; Chin Fong Chiu; Jer Lin

doi:10.1109/VLSI-DAT49148.2020.9196348

Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

Her-Ming Chiueh, Chia Hsiang Yang, Charles H.P. Wen, Chao Guang Yang, Po Hao Chien, Ching Yang Hung, Yu Jui Chen, Yao Pin Wang, Chin Fong Chiu, Jer Lin

研究成果: Conference contribution › 同行評審

摘要

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET \lt 101.5 MeV-cm {2} / mg), validating the effectiveness of the methodology.

原文	English
主出版物標題	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781728160832
DOIs	https://doi.org/10.1109/VLSI-DAT49148.2020.9196348
出版狀態	Published - 八月 2020
事件	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan 持續時間: 10 八月 2020 → 13 八月 2020

出版系列

名字	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
國家	Taiwan
城市	Hsinchu
期間	10/08/20 → 13/08/20

存取文件

10.1109/VLSI-DAT49148.2020.9196348

其它文件與鏈接

Link to publication in Scopus

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引用此

Chiueh, H-M., Yang, C. H., Wen, C. H. P., Yang, C. G., Chien, P. H., Hung, C. Y., Chen, Y. J., Wang, Y. P., Chiu, C. F., & Lin, J. (2020). Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. 於 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 [9196348] (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT49148.2020.9196348

Chiueh, Her-Ming ; Yang, Chia Hsiang ; Wen, Charles H.P. ; Yang, Chao Guang ; Chien, Po Hao ; Hung, Ching Yang ; Chen, Yu Jui ; Wang, Yao Pin ; Chiu, Chin Fong ; Lin, Jer. / Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020).

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title = "Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS",

abstract = "An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET \lt 101.5 MeV-cm {2} / mg), validating the effectiveness of the methodology. ",

author = "Her-Ming Chiueh and Yang, {Chia Hsiang} and Wen, {Charles H.P.} and Yang, {Chao Guang} and Chien, {Po Hao} and Hung, {Ching Yang} and Chen, {Yu Jui} and Wang, {Yao Pin} and Chiu, {Chin Fong} and Jer Lin",

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doi = "10.1109/VLSI-DAT49148.2020.9196348",

language = "English",

series = "2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020",

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Chiueh, H-M, Yang, CH, Wen, CHP, Yang, CG, Chien, PH, Hung, CY, Chen, YJ, Wang, YP, Chiu, CF & Lin, J 2020, Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. 於 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020., 9196348, 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Institute of Electrical and Electronics Engineers Inc., 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-DAT49148.2020.9196348

Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. / Chiueh, Her-Ming; Yang, Chia Hsiang; Wen, Charles H.P.; Yang, Chao Guang; Chien, Po Hao; Hung, Ching Yang; Chen, Yu Jui; Wang, Yao Pin; Chiu, Chin Fong; Lin, Jer.

2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9196348 (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020).

研究成果: Conference contribution › 同行評審

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AU - Wen, Charles H.P.

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AU - Chien, Po Hao

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AU - Chen, Yu Jui

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AU - Chiu, Chin Fong

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AB - An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET \lt 101.5 MeV-cm {2} / mg), validating the effectiveness of the methodology.

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BT - 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

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Chiueh H-M, Yang CH, Wen CHP, Yang CG, Chien PH, Hung CY 等. Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. 於 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9196348. (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020). https://doi.org/10.1109/VLSI-DAT49148.2020.9196348