Prospects for low-power, high-speed MPUs using 1.5nm direct-tunneling gate oxide MOSFETs

Hisayo Sasaki Momose*, Mizuki Ono, Takashi Yoshitomi, Tatsuya Ohguro, Shin Ichi Nakamura, Masanobu Saito, Hiroshi Iwai

*Corresponding author for this work

研究成果: Article同行評審

26 引文 斯高帕斯(Scopus)

摘要

The ability to operate 1.5 nm direct-tunneling gate oxide MOSFETs at low power and high speed with a low supply voltage in the 0.5 V range is investigated. We extrapolate the performance of current high-end MPUs assuming that conventional 0.4 μm MOSFETs are replaced by such direct-tunneling gate oxide MOSFETs. A simple estimate shows that the high current drive of direct-tunneling gate oxide MOSFETs may lead to MPUs which operate at frequencies several times higher than today's, while consuming several times less power.

原文English
頁(從 - 到)707-714
頁數8
期刊Solid-State Electronics
41
發行號5
DOIs
出版狀態Published - 五月 1997

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