Programming efficiency of stacked-gate flash memories with high-κ dielectrics

Y. Y. Chen*, Chao-Hsin Chien, K. T. Kin, J. C. Lou

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

The programming efficiency of high-permittivity (κ) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-κ IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2 as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical 10μs programming time. However, the effect of high-κ TDs was quite different when compared with high-κ IPDs. High-κ TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under 10μs programming time by choosing HfO2 as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-κ IPDs and TDs were suitable for next-generation NAND-and NOR-type stacked-gate flash memories, respectively.

原文English
主出版物標題NanoSingapore 2006
主出版物子標題IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings
頁面302-305
頁數4
DOIs
出版狀態Published - 14 十一月 2006
事件2006 IEEE Conference on Emerging Technologies - Nanoelectronics - Singapore, Singapore
持續時間: 10 一月 200613 一月 2006

出版系列

名字NanoSingapore 2006: IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings
2006

Conference

Conference2006 IEEE Conference on Emerging Technologies - Nanoelectronics
國家Singapore
城市Singapore
期間10/01/0613/01/06

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