Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Hao I. Yang*, Ching Te Chuang, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.

原文English
主出版物標題2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
頁面102-105
頁數4
DOIs
出版狀態Published - 20 八月 2010
事件2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 - Grenoble, France
持續時間: 2 六月 20104 六月 2010

出版系列

名字2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Conference

Conference2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
國家France
城市Grenoble
期間2/06/104/06/10

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