PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Chih Ting Yeh*, Yung Chih Liang, Ming-Dou Ker

*Corresponding author for this work

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

原文English
主出版物標題Electrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011
出版狀態Published - 10 十一月 2011
事件2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011 - Anaheim, CA, United States
持續時間: 11 九月 201116 九月 2011

出版系列

名字Electrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN(列印)0739-5159

Conference

Conference2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011
國家United States
城市Anaheim, CA
期間11/09/1116/09/11

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